1. Field of the Invention
The present invention relates in general to a semiconductor device or a semiconductor integrated circuit and a method of forming the same.
2. Description of the Prior Art
A variety of approaches have been carried out in order to miniaturize integrated circuits and achieve a higher packing density in a chip. Particularly, remarkable advances have been reported in the development of the technology to miniaturize insulated gate field effect semiconductor devices, denoted as MOSFET for short. MOS is the acronym of Metal. Oxide Semiconductor. The metal used in MOSFETs generally includes, in addition to genuine metals, conductive materials such as semiconductors having a sufficient conductivity, alloys composed of semiconductor(s) and/or metal(s). The oxide generally includes, in addition to genuine oxides, insulating materials having a sufficient resistivity such as nitrides. Although these materials do exactly not correspond to the acronym MOS, the term MOSFET is used in the broad sense in this description.
The miniaturizing of MOSFETs is realized by decreasing the width of the gate electrode. The decrease of the width of the gate electrode leads to the decrease of the channel length underlying the gate electrode. This also results in a high operational speed because the short channel length decreases the time required for carriers to pass across the channel.
The miniaturizing, on the other hand, gives rise to other problems, i.e. short channel effects. One of the most serious problems thereof is hot electron effects. In the structure comprising highly doped source and drain regions with an inversely doped intervening channel region therebetween, the strength of the electric field at the boundary between the channel region and the highly doped region increases as the channel length decreases. As a result, the characteristics of the device are unstable.
Referring to FIGS. 1(A) to 1(C), a prior art method of forming silicon gate MOSFETs is described. In the upper surface of a single crystalline semiconductor substrate such as a single crystalline silicon substrate 501, field insulating films are selectively formed by a suitable technique, e.g. LOCOS. The entire upper surface of the substrate is then oxidized by, e.g. dry thermal oxidation to form a gate insulating film 503. A gate electrode 505 of polysilicon is deposited on the gate insulating film 503. Impurity ions are introduced into the substrate by ion implantation with the gate electrode 505 as a mask in order to define source and drain regions as illustrated in FIG. 1(A).
Next, an interlayer insulating film 506 is formed from pure silicon oxide or phosphorus doped or boron doped silicon oxide as illustrated in FIG. 1(B), followed by opening contact holes 507 and 508 through the interlayer insulating film 506 and the silicon oxide film 503. Source and drain electrodes 509 and 510 are formed to make contact with the source region and the drain regions 504 as illustrated in FIG. (C).
As a result of the above process, there arise several problems. One problem is the disconnection of the source and drain electrodes or extensions thereof at the periphery of the contact holes 507 and 508 forming high and sharp steps. The height of the steps is determined substantially by the thickness of the interlayer insulating film 506 since the thickness of the gate insulating film 503 is very small as compared with that of the interlayer insulating film 506. The height is usually 200 to 500 nm and sometimes larger. This poses no problem when the diameter of the contact holes is relatively large. However, as the packing density integrated semiconductor devices in a chip increases, the diameter is required to be no larger than one micrometer while in the past contact holes of about 10 micrometers diameter were formed. On the other hand, the thickness of the interlayer insulating film is determined by tolerable capacitances among wirings and the dielectric characteristics of thereof so that it is impossible to furthermore decrease the thickness from the current level. As a result, the thickness of the interlayer insulating film can not be neglected as compared with the dimension of the contact holes and therefore it is often the case that necessary electrodes have not been formed completely inside the contact holes or have been disconnected because of poor step coverage and poor mechanical contact between the electrodes and the underlying surfaces.
Furthermore, as seen from FIGS. 1(A) and 1(C), impurity atoms necessarily go around under the gate electrode so that there is formed overlap therebetween resulting in an undesirable parasitic capacitance. Because of such overlap, a very strong electric field is applied to the gate insulating film, which is extremely thin, so that hot carriers tend to enter and be trapped in the gate insulating film.
The LDD (lightly-doped-drain) structure has been proposed to solve the above problem. This structure is schematically illustrated in FIG. 2(D). In the figure, reference numeral 604' designates a lightly doped region formed inside of a heavily doped region 605. The region 604' is called a LDD region. By provision of such a LDD region, the strength of the electric field in the vicinity of the boundary between the channel region and the drain region is decreased so that the operation of the device becomes more stable.
FIGS. 2(A) to 2(D) are cross sectional views showing a method of making a conventional MOSFET having a LDD structure. Although an n-channel transistor is explained here, a p-channel transistor is formed in the same manner simply by inverting the conductivity type. Namely, field insulating films 602 are first formed on a p-type silicon semiconductor substrate 601 as device separating regions in order to insulate each from other active regions (only one being shown in the figure) in which devices are fabricated. A gate insulating oxide film 603 and a conductive film are deposited on the semiconductor substrate and patterned by etching in order to form a gate electrode 605 insulated by the gate insulating film 603. With the gate electrode 605 and the field insulating films 602 as a mask, lightly doped regions 604 of an n- conductivity type are formed by ion implantation in a self-aligning fashion.
Next, the structure is coated with an insulating film 606 such as a PSG film. The insulating film 606 is removed by an anisotropic etching (directional etching) such as bias plasma etching, leaving spacers 607 flanking the side walls of the gate electrode 605. With the spacers 607 as a mask, heavily doped regions 605 of an n+conductivity type are formed by ion implantation to provide source and drain regions, leaving LDD regions 604'. By employing this LDD design, the channel length can be decreased to as short as 0.1 micrometer while the channel length in usual designs can not be decreased to 0.5 micrometer or shorter.
The problems associated with such short channel designs, however, are not completely solved even by this technique. Another problem is the resistance of the gate electrode which has become narrow as a result from the decrease in channel length. Even if the switching speed of the device is increased by the short channel, the speed-up effects may possibly come to naught due to propagation delay along the high resistant gate electrode. The resistance of the gate electrode can be decreased to some extent by employing a metal silicide having a low resistivity in place of polysilicon to form the gate electrode or by providing a low resistant line such as an aluminum line extending along the gate electrode. These techniques, however, can not deal with the high resistance problem when the width of the gate electrode is no larger than 0.3 micrometer.
Another approach to solve the problem is to increase the aspect ratio of the gate electrode, i.e. the ratio of the height to the width of the gate electrode. The resistance of the gate electrode decreases in proportion to the cross sectional area which increases as the aspect ratio increases. From the view point of manufacture restraints, the aspect ratio can not be increased so much. This is mainly because the width of the spacers depends on the height of the gate electrode. The spacer is necessarily formed with its width of 20% or wider of the height of the gate electrode. Accordingly if 0.1 micrometer width L of the LDD region 604' (FIG. 2(D)) is desired, the height of the gate electrode can not exceed 0.5 micrometer. If the gate electrode has a height exceeding 0.5 micrometer, the width L exceeds 0.1 micrometer resulting in a higher resistance between the source and drain regions.
In the case of 0.5 micrometer height (H), 1.0 micrometer width (W) and 0.1 micrometer width (L) in FIG. 2(D), if the width (W) of the gate electrode is desired to be increased to 0.5 micrometer for further miniaturizing, the height of the electrode must be increased to 1.0 micrometer in order to avoid increase of the gate resistance. The width (L) of the spacers, however, becomes 0.2 micrometer so that the resistance between the source and drain regions with the FET being turned on is doubled. The halved channel length is expected to improve double the operational speed. The increase of double the source and drain resistance, however, cancels the improvement. Accordingly, the operational speed remains same as achieved before the shrinkage in size. On the other hand, if the width L is maintained at the conventional level, the height H must be 0.5 micrometer which makes double the resistance of the gate electrode, resulting in no improvement on the operational speed.
Usually, the width of the spacer becomes as wide as 50% to 100% of the height of the gate electrode, which width provides a further severe condition. The aspect ratios of the gate electrodes, therefore, have been no higher than 1, or in many cases no higher than 0.2 in accordance with the conventional LDD technique. In addition to this, the width of the spacer has been substantially dispersed, due to expected variations of production, which results in dispersed characteristics of the products. The conventional LDD technique has brought high integrations and high speeds and, on the contrary, impeded further improvement.
Of course, the problem of disconnection of wirings at step-wise boundaries of contact holes can not be solved since, also in the LDD technique, an interlayer insulating film is coated and contact holes are opened therethrough, followed by coating electrodes and wirings thereover in order to make electric contact with the underlying regions.